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AUX Bus Pin

The Aux bus pin has several modes of operation

Wait/Ready (!ACK)

In this mode, the pin is device managed. It is used for devices which can provide ready/ack statuses which is a means to control speed. This could be fast or slow, but is more of an async mode since neither the bus controller nor card need to strictly follow the bus clock.

States

!ACK Low: Device is not done with task or is waiting on a task. Default state. !ACK High: Indicates device is done with task.

Setup

The Device uses !DS# to control a tri-state buffer which is tied to the internal !ACK pin. By default, it should keep this pin low when not in a transaction. This is so the bus controller starts in a waiting state until the device actively responds back.

Devices which support this mode must have a watchdog timer to reset themselves on error. This can be coupled with a "max wait" timeout configured (either per device or global) as part of the system configuration (which is stored on the MCU and read during boot-up). When max wait is exceeded, the bus controller gives up, de-asserts !W, !R, !DS# and raises an interrupt with the CPU for any recovery steps.

Because the System MCU is also on the bus, a frozen bus state may be unrecoverable as the MCU would be unable to issue a !RESET. The device watchdog is, therefore, the last line of defense against an unrecoverable bus lockup. The reason for !RESET being managed by the MCU is strictly due to pin availability on the FPGA (CPU/SOC/Bus Controller) for the current iteration of the Turbo V.

"May" is doing work here. There are good design decisions on building cards to be more tolerant of failed states from things like MCUs. Using a 74HC245/541 and 74HC00/138 can help make cards more resilient, though the details are not for this doc.

Example Transactions

This requires abiding by a strict sequence which is as follows:

Single Data Read

This is the bus controller needing to read a single byte at an address from the device. There are other possible scenarios for multi-byte reads (CPU needs to read a word) or for striding (bulk sequential reading).

  1. Device holds local !ACK pin low, the bus side remains high-Z until !DS# enables the tri-state buffer.
  2. Bus Controller sets up the address, sets AUX mode to !ACK (pin set to input)
  3. Bus Controller asserts !R
  4. Bus Controller waits for address settling time, then asserts !DS#
  5. Tri-state is active, so !ACK becomes low on the bus. Device sees !DS# and !R and begins work.
  6. Device presents data onto the data lines
  7. Device waits for settling time, then sets !ACK to high indicating it is done.
  8. Bus Controller sees !ACK is high, so it reads (latches) the data then de-asserts !R and waits.
  9. When device sees !R has been de-asserted, it sets !ACK back to low and releases the data-lines
  10. When the Bus Controller sees !ACK is low, de-asserts !DS#

Strobe (!STB)

Useful for devices that need a strobe but not necessarily a full clock. This can be useful for devices which cannot operate with the bus clock as a strobe (due to speed or otherwise). Example use case would be a slower UART.

Second Clock (CLK2)

Much like strobe, but is a 2nd bus clock that is derived from the CPU clock. It can be used for fast or slow devices which need a clock.

High Address (A19)

This provides A19 to the device which doubles the address space and is useful for things like parallel flash ROM or SRAM.