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CPU, SOC and Bus Controller

In the current hardware design, the CPU, SOC and Bus Controller all run on a single device. An Upduino FPGA development board which houses an ICE40 FPGA with some additional nice to haves.

Core

Core will be the FemoRV Gracilis (RV32IMC + irq) or PetitBateau (RV32IMFC + irq) with a current target clock speed of 48 MHz, though hard numbers for the ICE40 variant have not been validated. It may be as low as 12MHz. This needs to be tested/validated with tooling and tested on real hardware.

Features:

  • 5.3k LUTs
  • 128KB SRAM (Used for Low RAM and the User Stack)
  • 15KB DPRAM (Dual Port RAM, for kernel traps, vectors, etc.)
  • USB UART (Debugging)
  • Lots of Flash (currently not used except to bring up the FPGA itself)

Upduino GPIO Pin Requirements

Signal Count Purpose
A18–A00 19 19-bit Address
D7–D0 8 Data
DS2-DS0 3 Device Select 74HC138
!R 1 Read Request
!W 1 Write Request
!IRQ 1 Global Interrupt
AUX 1 Multi Function

Total: 34

12 MHz Clock is available on a separate pin and is both connected to the bus directly and is internally routed to the FPGA (for use with the PLL or to directly clock the CPU also).

Upduino Physical Pin Map

            PCF  Pin#  _____  Pin#  PCF
                 ------| USB |------
           <GND> |  1   \___/   48 | spi_ssn   (16)
           <VIO> |  2           47 | spi_sck   (15)
           <RST> |  3           46 | spi_mosi  (17)
          <DONE> |  4           45 | spi_miso  (14)
DS0      led_red |  5           44 | gpio_20   12 MHz CLOCK
DS1    led_green |  6     U     43 | gpio_10
DS2     led_blue |  7     P     42 | <GND>
           <+5V> |  8     D     41 | <12 MHz>
         <+3.3V> |  9     U     40 | gpio_12
           <GND> | 10     I     39 | gpio_21
         gpio_23 | 11     N     38 | gpio_13
         gpio_25 | 12     O     37 | gpio_19
         gpio_26 | 13           36 | gpio_18
         gpio_27 | 14     V     35 | gpio_11
         gpio_32 | 15     3     34 | gpio_9
<G0>     gpio_35 | 16     .     33 | gpio_6
         gpio_31 | 17     0     32 | gpio_44   <G6>
<G1>     gpio_37 | 18           31 | gpio_4
         gpio_34 | 19           30 | gpio_3
         gpio_43 | 20           29 | gpio_48
         gpio_36 | 21           28 | gpio_45
         gpio_42 | 22           27 | gpio_47
         gpio_38 | 23           26 | gpio_46
         gpio_28 | 24           25 | gpio_2
                 -------------------

Bus Termination

I could not find a good answer on if/how this might be an issue (ringing). It might be wise to consider adding places for series resistor packs so they can be added if needed. This or lowering the bus speed.

Simulation Tests:

These numbers are actually flawed. Later tests show the CPU may end up being closer to 12-18MHz. Or at least needs to be properly simulated with Lattice tools.

Quark: 62 MHz Electron: 71 MHz Intermissum: 71 MHz Gracilis: 36 MHz PetitBateau: 36 MHz

  • https://www.youtube.com/watch?v=rvhDyJVuAzk
  • https://www.youtube.com/watch?v=bEUMLh2lasE&list=PLp_QNRIYljFqBuOYDFluT66Y7biUH1Dnc
  • https://projectf.io/posts/riscv-jump-function/#stack
  • https://tinyvision.ai/products/fpga-development-board-upduino-v3-1
  • https://github.com/YosysHQ/icestorm/wiki/iCE40-PLL-documentation
  • https://github.com/XarkLabs/upduino-example/blob/master/UPduino_V3.x_Pins.md
  • https://projectf.io/isle/riscv-cpu.html
  • https://www.eevblog.com/forum/projects/timing-constraints-in-open-workflow-for-ice40up5k/