CPU, SOC and Bus Controller
The CPU, SOC and Bus Controller run on an Upduino which is housed on a card right above the power board.
Core
Core will be the FemoRV PetitBateau (RV32IMFC + irq)
Features:
- 5.3k LUTs
- 128KB SRAM (Low Mem)
- 15KB DPRAM (Dual Port RAM, for kernel traps, vectors, etc.)
Upduino Pin Requirements
| Signal | Count | Purpose |
|---|---|---|
| A18–A00 | 19 | Address |
| D7–D0 | 8 | Data |
| DS2-DS0 | 3 | Device Select 74HC138 |
| RW | 1 | Read/Write Request |
| !IRQ | 1 | Global Interrupt | | Clock | 1 | Bus Clock |
Total: 34
Upduino Physical Pin Map
PCF Pin# _____ Pin# PCF
------| USB |------
<GND> | 1 \___/ 48 | spi_ssn (16)
<VIO> | 2 47 | spi_sck (15)
<RST> | 3 46 | spi_mosi (17)
<DONE> | 4 45 | spi_miso (14)
RESET led_red | 5 44 | gpio_20 <N/A w/OSC, G3>
!IRQ led_green | 6 U 43 | gpio_10
<RGB1> led_blue | 7 P 42 | <GND>
<+5V> | 8 D 41 | <12 MHz>
<+3.3V> | 9 U 40 | gpio_12
<GND> | 10 I 39 | gpio_21
gpio_23 | 11 N 38 | gpio_13
gpio_25 | 12 O 37 | gpio_19
gpio_26 | 13 36 | gpio_18
gpio_27 | 14 V 35 | gpio_11
gpio_32 | 15 3 34 | gpio_9
<G0> gpio_35 | 16 . 33 | gpio_6
gpio_31 | 17 0 32 | gpio_44 <G6>
<G1> gpio_37 | 18 31 | gpio_4
gpio_34 | 19 30 | gpio_3
gpio_43 | 20 29 | gpio_48
gpio_36 | 21 28 | gpio_45
gpio_42 | 22 27 | gpio_47
gpio_38 | 23 26 | gpio_46
gpio_28 | 24 25 | gpio_2
-------------------
Bus Termination
I could not find a good answer on if/how this might be an issue (ringing). It might be wise to consider adding places for series resistor packs so they can be added if needed. This or lowering the bus speed.
Useful Links:
- https://www.youtube.com/watch?v=rvhDyJVuAzk
- https://projectf.io/posts/riscv-jump-function/#stack
- https://tinyvision.ai/products/fpga-development-board-upduino-v3-1