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Memory Map

The system has an internal 32-bit address space. This space is carved up as follows:

31-24 23-20 19-00
Segment Function Data

The reason is, this system being a baremetal retro machine is likely to never have a crazy amount of RAM where we would want 2GB or more of contiguous space. So the address space can be carved up to make things a little more logical and easier for the developer. This includes remapping things like physical memory cards on the Turbo Bus to a specific segment. This makes future expansion (hopefully) more elegant.

Layout

The list below is a bit of a hodgepodge of full allocation and current hardware allocation, but gives hopefully an idea of how this is intended to work.

Note that Turbo Bus is a 24-bit bus, so the addresses include the Device and Data and maps nicely to physicaly devices.

Segments:
  User RAM (Segment 00):
    Low RAM (SRAM), 112K:                           00 0 00000..00 0 1BFFF
    User Vars (DPRAM), 1K                           00 1 00000..00 1 003FF
    Main/Bus RAM (Device 0 Mirror)                  00 2 00000..00 2 FFFFF
  System RAM (Segment 01):
    Kernel Vars (DPRAM), 1K:                        01 1 00000..01 1 003FF
    System Traps & Vectors (DPRAM), 4K:             01 0 00000..01 0 00FFF
    IRQ Stack (DPRAM), 4K:                          01 E FF000..01 E FFFFF
    Stack RAM (SRAM), 16K:                          01 F FC000..01 F FFFFF
  Banked RAM (Segment 02):
    Bank RAM 0 (Device 2 Mirror), 256k              02 0 00000..02 0 3FFFF
    Bank RAM 1..14 (Reserved)                       02 1 00000..02 E FFFFF
    Page Registers:                                 02 F 00000..02 F FFFFF
      Bank 0 Page Register (Device 2 Mirror):       02 F 00000..02 F 00001
      Bank 0 Num Pages (Device 2 Mirror):           02 F 00002..02 F 00003
      Bank 0 Page Size (Device 2 Mirror):           02 F 00005..02 F 00008
  ROM (Segment 03):
    Kernel ROM (Device 1 Mirror):                   03 0 00000..03 0 FFFFF
    (Reserved, Option ROMs)
    Game Cart ROM (Device 15 Mirror):               03 F 00000..03 F FFFFF
  8-bit Turbo Bus (Segment F0):                                  
    Device 0 (System RAM, Up to 1MB):               F0 0 00000..F0 0 FFFFF
    Device 1 (Kernel ROM, Up to 1MB):               F0 1 00000..F0 1 FFFFF
    Device 2 (MCU):                                 F0 2 00000..F0 2 FFFFF
      Banked Smart RAM (256k):                      F0 2 00000..F0 2 3FFFF
      Reserved (512k):                              F0 2 40000..F0 2 BFFFF
      System Registers (128k):                      F0 2 C0000..F0 2 DFFFF
      Smart RAM Registers (128k)                    F0 2 E0000..F0 2 FFFFF
    Device 3 (Video/VERA/User):                     F0 3 00000..F0 3 FFFFF
    Device 4 (User):                                F0 4 00000..F0 4 FFFFF
    ...
    Device 15 (Cartridge ROM):                      F0 F 00000..F0 F FFFFF
  Internal FPGA System Bus (Segment FE):
    FemtoRV USB UART Data, 4B:                      FE 0 00000..FE 0 00003
    FemtoRV USB UART Control, 4B:                   FE 0 00004..FE 0 00007
  Global System Registers (Segment FF):
    System Setup (DPRAM or LUTs), 1K:               FF 0 00000..FF 0 003FF
      CPU Clock Divisor:                            FF 0 00000..FF 0 00000          
      Bus Clock Divisor:                            FF 0 00001..FF 0 00001
      Turbo Bus Wait States, 16 bytes:              FF 0 00010..FF 0 0001F
    MCU System Registers (Device 2 Mirror), 128K:   FF 1 00000..FF 1 1FFFF

In the current hardware proposal, SRAM, DPRAM and LUTs run at CPU speed which means the remapped devices, of course, run at the speed of the Turbo Bus.

Device Remapping

To make it easier for the user/developer and allow for at least attempting future expansion and upgrades, some things are remapped. Notably in the minimal config, the MCU has a window of banked Smart RAM. If a user wants to add a bigger RAM card, they could place it at Bank RAM 0. This will come from the system config which will be stored in MCU flash or on the MCU SD Card.

How this works with the current FPGA (Upduino) in terms of LUT usage remains TBD.

Game Cartridge

Game Cartridge ROM is available in the ROM segment. At present it is remapped from special Device 15 on the TurboBus. This is so future cartridges on other busses could be used though in practice the Game Cart ROM area is special. If a cartridge is available here, it will cause the system to boot direct to the cartridge (though this can be disabled via boot settings in the MCU). This can be automagic given cartridges will need to provide a "CART" header as the first 4 bytes of the memory area. If the system finds this, and is set to auto-boot to carts, it will boot into the cart by jumping to the remapped address (0x03F00000).