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Turbo Bus

  • A18-A00 19-bit address
  • D7-D0: 8-bit data
  • !DS7-DS0: Device Select
  • !R: Low active read
  • !W: Low active write
  • !IRQ: Low active global IRQ
  • !RES: Low active reset (comes from MCU)
  • CLK: 12 MHz bus clocke (from Upduino)
  • AUX: Multi-function
    • !ACK: Ack (wait/ready) for slow / async devices
    • !STB: Strobe for things like slow UARTs
    • CLK2: Configurable 2nd clock for fast or slow clocked devices
    • A19: 20th address bit for 1MB data window for things like SRAM

Pin Descriptions

A18-A00: Address Bus

19-bit address bus which allows for up to 512k in a flat memory space.

For some cards this is broken in half into register/commands and memory space (256k each).

D7-D0: Data Bus

8-bit data lines

!DS7-DS0: Device Select

Device Select ("Chip Select") to indicate which device the bus controller is talking to. Decoded from 3 pins on the FPGA to a decoder. Avoids complicated logic for settling time when doing device coding via addressing alone and is meant to allow for both fast and slow cards to participate on the bus.

This means only one !DS pin is active at any given time.

!R: Read Request

Active low, indicates CPU is requesting a read from device. For smart devices, strobbing allows for bulk/stride reads.

!W: Write request

Active low, indicates CPU is requesting a write to device. For smart devices, strobbing allows for bulk/stride writes.

AUX: Multi-Use (!ACK, !STB, CLK2, A19)

Bidirectional pin which has multiple use cases depending on the device type:

  • Wait/Ready (!WAI): Output.
    • Used for slow bus devices (like slow 8-bit microcontrollers)
    • Used for stalls like a page flip for banked smart RAM
  • Strobe (!STB): Input. Used for slower devices (like !ADS on slow UARTs)
  • Second Clock (CLK2): Input. Second independent clock derived from CPU clock
    • Used for fast devices that can run faster than the bus, but which must be clocked
    • Used for slower devices that need a clock slower than the main bus clock
  • Address (A19): Input. High address pin to double the address space (1MB)
    • For SRAM or ROM

AUX is more involved so for more details, see Aux

!RESET: System Reset

Active low. To save on pins on the FPGA, the reset signal is tied to the MCU, although technically any device could assert this. This should cause all devices on the bus to reset to power-on state.

!IRQ: Global Interrupt

Active low interrupt assertion. When low, it signals to the system the device is asserting an interrupt. This is open drain and the motherboard has a pull-up resistor.

Being a global interrupt, any device can assert this and the CPU/interrupt routine will need to figure out which device it is.

Clock: Bus Clock

The bus clock, which is a divisor of the CPU clock. Targeting 12 MHz as this means the Upduino clock can be used directly, although 24 MHz might be more ideal. For intelligent devices, like MCUs, the clock is optional. Communication happens via !DS, !R, !W, and COM. This is because slow MCUs might not be able to keep up with the clock at all.

Devices which require timing though obviously have to accurately observe the clock (such as shift registers, etc.).

Note that while the clock is fixed, the bus controller has configurable per card wait states to relax timing. This is largely for devices without MCUs, such as regular RAM or ROM chips, for when they could not otherwise keep up with full speed timing and cannot assert !RDY.