Turbo V
The Turbo V is a (for now) hypothetical bare-metal retro-inspired computer which runs a RISCV soft-core on an ICE40 FPGA. It is lovingly inspired by the Commander X16 with a similar mission and design, but with some changes to fit the FPGA architecture and 32-bit platform, along with necessary modern constraints due to availability of through hole chips and cost containment.
Contents:
Loose High Level Specs
- CPU: FPGA-based RV32IMC RISC-V core (FemtoRV on iCE40 UP5K) at 12-24 MHz
- Backplane-Like Design
- 112 KB Internal SRAM (Application RAM)
- 512 KB Boot ROM
- 1MB Bus RAM
- 8MB Banked RAM
- Expansion Bus:
- Multiple modes (clocked, async, fast-clock)
- 19-bit address / 8-bit data
- 512 KB per-device window optionally split into control/data segments
- 8-bit bank latch in control window -> 64 MB addressable per device
- Per device bus divisors
- 8 device selects via 74HC138 (3-to-8) - 6 expansion slots + ROM + system controller
- Single shared IRQ (nIRQ), active-low open-drain
- Interrupts: PicoRV32 custom mechanism (PC saved to q0, return via retirq)
- Per-slot dedicated stereo returns (mixed on the motherboard)
- -/+ 12V and 3.3V rails
- Repurposed PCIe connectors
- I/O MCU (RP2350, PGA2350)
- USB keyboard/mouse
- SNES controllers
- SD card storage
- Timers
- User Flash Storage (Boot Options, etc.)
- Video/Audio: VERA on expansion card (primary video + PSG/PCM audio)
- Audio: TurboWave on expansion card (optional)
Resources
Current State
- Working emulator based on rv32emu with VERA integration
- Minimal Kernel
- Partial memory map implementation in the emulator
- Stefan's BASIC (textmode)
TODO
So so much :)
- tvproject - reference project design for writing RISCV asm apps for the Turbo V
- Default kernel ISR with emulator support
- Address aliases is emulator
- Text drawing routines for the kernel
- Pondering helper routines for graphics in the kernel as an API in front of VERA
- Juggling layers and such could get messy when I did it on the X16
- You know, hardware.