Turbo V
The Turbo V is a (for now) hypothetical bare-metal retro-inspired computer which runs a RISCV soft-core on an ICE40 FPGA. It borrows some fundamental design ideas from the Commander X16 but with some changes to fit the FPGA architecture and 32-bit platform, along with necessary modern constraints due to availability of through hole chips.
This is just a fun thought exercise for now. Assuming the hardware actually can work, there is no kernel.
Contents:
Loose High Level Specs
- CPU: FPGA-based RV32IMC RISC-V core (PicoRV32 on iCE40 UP5K) at ~48 MHz
- 128 KB zero-wait FPGA SPRAM (internal system RAM)
- 256 B internal FPGA boot ROM (reset vector -> jump to system ROM)
- 512 KB motherboard flash ROM (flat mapped, A0-A18 direct)
- Expansion Bus:
- 12 MHz
- 19-bit address / 8-bit data
- 512 KB per-device window optionally split into control/data segments
- 8-bit bank latch in control window -> 64 MB addressable per device
- Per device bus divisors
- 8 device selects via 74HC138 (3-to-8) - 6 expansion slots + ROM + system controller
- Single shared IRQ (nIRQ), active-low open-drain
- Interrupts: PicoRV32 custom mechanism (PC saved to q0, return via retirq)
- Per-slot dedicated stereo returns (mixed on the motherboard)
- -/+ 12V and 3.3V rails
- Repurposed PCIe connectors
- I/O MCU (RP2350, PGA2350)
- USB keyboard/mouse
- SNES controllers
- SD card storage
- Timers
- User Flash Storage (Boot Options, etc.)
- Video/Audio: VERA on expansion card (primary video + PSG/PCM audio)
- Audio: TurboWave on expansion card (optional)
Contributions and Clarity
I want to be clear what tools and resources I used to help ratify the design. I have had the basic design in my head for quite a while but it had gaps that needed clarification. This includes the use of AI tools to help with brainstorming, part finding, searching, etc. Specifically I used Kagi's AI assistant (specific Kimi K2.6) to brainstorm. I did not use AI to write any code or any of this documentation.