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Smart RAM Expansion

While there can be many types of RAM expansion cards, to help standardize on design, this is a proposal for a card that would serve as main memory while housing something like an MMU on board for enhanced interactions.

Since it is on the bus, it will run at bus speeds of course, and not be nearly as fast as the SRAM on the FPGA core. This is doubly true if the bus speed ends up being fairly high (12 MHz) where wait states might be required.

The command registers are used largely to control banking. Since there is such a large command space, a suggested allocation is below. The Bank select is a 16-bit value supporting up to 65k pages which equates to a staggering 16GB, which is unlikely any card would use. The second set of registers is a read-only value which tells the system how many pages are actually available of the total.

Most cards will probably have <=256 banks given this is 64MB and that is still plenty.

It should be noted that there can technically be multiple RAM cards in the system for whatever reason. The suggested address layout does not account for this given a vast majority of users will only have a single RAM card.

Burst mode is a future idea which would allow for faster transfers when leveraging PSRAM.

The rest of the docs will largely reference the lower 19-bit address range, though the full range is as follows:

  • Command: 0x40040000..0x4007FFFF
  • Data: 0x40000000..0x4003FFFF

Where 0x4... is the recommended device range for RAM if it is the only RAM card (0x5 otherwise). This isn't hard set, though any given system should probably have at least one RAM card of some type.

Command/Registers

Command Registers occupy the top half of the address range and are for behavior or special access conditions (such as stride). The bottom half of the address range is for direct access to memory.

Table

Address Function Scope
0x40000..0x40001 Page Sel RW
0x40002..0x40003 # Pages RO
0x40004 Support RO
0x40005 Status RO
0x40006 IRQ Enable RW
0x40007 IRQ Clear WO
0x40008..0x40009 Stride Address WR
0x4000A Stride Config WR
0x4000B Stride RW WR

Description

  • Page Select, RW: 2 Bytes

    Select the page/bank for the lower 256k of RAM. Most cards will have <256 banks so once the system reads the bank number (below) it can change banks with a single 8-bit write in those cases. Cards which support more than 256 banks will need to solve for cases where the system changes the full page vs a partial. If the system writes to the high byte first, the card should know not to change the bank until the low byte is written.

  • Number of Pages, RO: 2 bytes

    Reports the number of 256k pages available, effectively telling the system how much RAM there is.

  • Support, RO: 1 byte,

    Speed rating of the card, which corresponds to the recommended wait-state to configure in the system setup as well as support flags.

    • Bit 7: Busy On Page Flip - if busy status is report on page flips

      If this is zero, it means the card can flip pages within the suggested wait state time If one, it means there can be page stalls longer than the wait state and should be checked before reading or writing the page.

    • Bit 6: IRQ Support - if card can assert IRQs for certain states

    • Bit 5: Stride Support - whether the card supports stride sequential reads/writes
    • Bit 4: Invalid Page Support - whether card will report a read error when reading past available pages
    • Bit 3: Writeback Support - whether card has a write/sync cache to lower page flip penalties
    • Bit 2..0: Recommended wait state divisor

  • Status, RO: 1 byte

    Status register for polling IRQ states or, if not using IRQs, checking for when low RAM is available for use. This is primarily for cards which require multiple clock cycles to deal with page changes.

    Mask:

    • Bit 7: IRQ For Page Ready
    • Bit 6: Invalid Page
    • Bit 5: Page Flip In Progress
    • Bit 4: Writeback In Progress
    • Bit 1: Generic Error
    • Bit 0: Busy

  • IRQ Enable, RW: 1 byte

    Enable various IRQs.

    • Bit 7: Enable IRQ for Page Ready
    • Bit 6: Enable Invalid Page
    • Bit 5: Enable Page Flip Notice (For Striding)
    • Bit 4: Writeback In Progress
    • Bit 1: Enable Generic Error
    • Bit 0: Enable Busy

  • IRQ Clear, WO: 1 byte

    Writing any non-zero value clears the IRQ assertion though note certain IRQ configurations and states would cause it to refire. Setting an IRQ on Page Flip or Busy, for instance, will refire until it finishes what it is doing.

  • Stride Address, RW: 2 bytes

    Where to start the stride RW. Note this is the lower address range and does not account for the page. Be sure to set the start page as required and be aware the page. Reading from this register will provide the address the stride is at.

  • Stride Enable, RW: 1 byte

    • Bit 7: Enable automatic page flipping
    • Bit 6..0: Stride Skips

    Set the stride value. If 0, do not stride (reading/writing to the slide register does not increment). Values greater than 1 automatically advance to the next address by that many hops. So 1 = next address. Setting Bit 7 enables automatic page flipping though note this can cause a stall on page boundary and should be planned for accordingly.

  • Stride Register, RW: 1 byte

    Read or write data to/from stride. Note reading or writing will both advance the stride position.

Case Study: Using a Pimoroni PGA2350

The PGA2350 has 8MB of PSRAM. This has fast sequential access, but can have slow random access. It also has 520k of fast SRAM. Half of this SRAM can be used as an active page cache. This should give us predictable access (to be determined what the wait-state value would need to be) except when flipping a page.

A page flip would be a significant stall as the system would need to copy the cache page back to PSRAM and then load the requested page from PSRAM into SRAM. Stall. However, the PGA2350 is cheap. Stall is made shorter by using the 2nd core to sync writes from the live page back to PSRAM as a sort of write-back kind of cache.

This makes it a good candidate for data storage, but perhaps not a great candidate for code though it depends on how jumpy the application itself is. Thinking about a tracker, for instance, the page flip penalty might be long enough to cause play stalls without a buffer in system RAM of some sort though this should be tested.

Related to the tracker scenario though, the PGA2350 can support essentially all the features outlined above for Smart RAM and that includes stride such that, at least in between page flips, accessing data can be quite fast which could be useful for sample loading, burst loading a pattern, etc.